1. Technical Field
The embodiments herein generally relate to wireless technologies, and, more particularly, to Digital Video Broadcasting over Handheld (DVB-H) technologies.
2. Description of the Related Art
A DVB-H device transmitter employs a Multi-Protocol Encapsulator Forward Error Correction (MPE-FEC) framing scheme, which uses a Reed-Solomon (RS) encoder along with an interleaver to provide protection from burst errors caused by impairments in the communication channel. In DVB-H receivers, a RS decoder and deinterleaver are required in the MPE-FEC processing unit to recover the transmitted data. The MPE-FEC RAM in the deinterleaver stores an entire MPE data frame, which, at maximum, has a size of 1024 rows by 255 columns data bytes. The RS decoder performs error correction on these received data row-by-row. With the “erasure” information, which is derived from the received IP datagrams and marks the possible error locations, the RS decoder doubles its error correction capability over a correction mode where these “erasure” locations are not available. However, the requirement of an additional large memory to store the erasure location increases the silicon area and power consumption of the DVB-H receiver.
The MPE-FEC process in the DVB-H receiver is generally as follows:
1. Received Internet Protocol (IP) datagrams are written into the MPE-FEC RAM column-by-column by the Transport-stream packet de-multiplexer (TS demux).
2. The cyclic redundancy check (CRC) is calculated for each received IP datagram and is compared to the CRC bytes at the end of each datagram. If the CRC matches, every data byte in this IP datagram is error free. Mismatched CRC indicates at least one or more bytes in this datagram being corrupted and, as a result, every byte in this datagram is marked as “erasure” indicating possible error locations. The “erasure” location information is stored in a column-wise manner in line with the order the datagrams are received.
3. After an entire MPE frame is filled, data are read from the MPE-FEC RAM row-by-row into the RS decoder with erasure information of each byte in each row. This allows the RS decoder to correct up to 64 error bytes.
4. The RS decoder output is written back to the MPE-FEC RAM row-by-row.
5. The corrected IP datagrams are read from the RAM column-by-column for post-processing and output.
The first challenge to store the erasure location is the large size of memory required. In a straightforward implementation, one bit is required for each data byte in the MPE-FEC frame RAM to flag the erasure. That requires 255×1024=255 Kbits of memory. In an indirect indexing implementation where the starting address of each IP datagram and its CRC status is stored, one would typically need a memory to hold such information for maximum number of IP datagram per frame. In this case, the total required memory is ┌log2 (255×1024)┐+1=18+1 bits (MPE-FEC RAM address range per frame+one bit CRC status) by (255×1024)/64=4080 (maximum number of IP datagram per frame since the minimum size of IP datagram is 64 bytes), which amounts to 76 Kbits per frame. In the design capable of processing multiple back-to-back DVB-H channels, one needs a MPE-FEC RAM larger than one frame and this erasure location cache memory also has to be increased proportionally.
The second challenge is to implement this erasure location cache RAM with an efficient addressing scheme for both column-wise and row-wise access since the erasure information is derived and stored in column-wise order but to be read into the RS decoder in row-wise order. An efficient scheme would allow both column-wise and row-wise accesses with simple address calculation within a single clock cycle therefore facilitating a high-throughput RS decoder, which, in turn, is essential for minimizing the MPE-FEC RAM size for a design capable of serving back-to-back DVB-H channels.
Two known methods to store the erasures for the MPE-FEC frame are direct-mapping and indirect-indexing. The direct mapping implementation is as follows: storing one erasure status bit for each data byte in the MPE-FEC frame RAM. This requires a minimum of 255×1024=255 Kbits of memory (for a single frame), and for a design capable of processing multiple frames back-to-back this number must be increased proportionally to the MPE-FEC RAM size. The indirect indexing implementation is as follows: in this case the starting address of each IP datagram and its CRC status is stored. This requires ┌log2(255×1024)┐+1=18+1 bits of memory for one IP datagram (MPE-FEC RAM address plus one bit CRC status). Since the minimum size of an IP datagram is 64 bytes, the maximum number of IP datagrams per frame is (255×1024)/64=4080. Thus the total memory requirement is 76 Kbits per frame (or a greater number when multiple frames are supported). The main difficulty with this approach is the fact that the erasure information is stored in MPE-FEC frame column order but processed by the RS decoder in the row order. Finding the erasure value for a particular data byte in row order is a complicated operation involving multiple erasure cache accesses and arithmetic calculations, which reduces the speed of RS decoding and greatly increases the complexity of the design. Moreover, for a design using circular MPE-FEC RAM access it would create additional complexities in erasure cache update logic, as there is no direct mapping between MPE-FEC RAM and corresponding erasure cache values. Accordingly, there remains a need for a novel erasure location cache memory technique.